Function core::arch::riscv64::aes64esm

pub unsafe fn aes64esm(rs1: u64, rs2: u64) -> u64

🔬This is a nightly-only experimental API. (stdsimd #48556)

Available on RISC-V RV64 and target feature zkne only.

AES middle round encryption instruction for RV64.

Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the ShiftRows, SubBytes and MixColumns steps. This instruction must always be implemented such that its execution latency does not depend on the data being operated on.

Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions

Version: v1.0.1

Section: 3.8

Safety

This function is safe to use if the zkne target feature is present.