Module core::arch::riscv64

🔬 This is a nightly-only experimental API. (stdsimd #27731)

Available on RISC-V RV64 only.

Platform-specific intrinsics for the riscv64 platform.

See the module documentation for more details.

Functions

fence_i^⚠Experimental

Generates the FENCE.I instruction

frcsrExperimental

Reads the floating-point control and status register fcsr

frflagsExperimental

Reads the floating-point accrued exception flags register fflags

frrmExperimental

Reads the floating-point rounding mode register frm

fscsrExperimental

Swaps the floating-point control and status register fcsr

fsflagsExperimental

Swaps the floating-point accrued exception flags register fflags

fsrmExperimental

Swaps the floating-point rounding mode register frm

hfence_gvma^⚠Experimental

Hypervisor memory management fence for guest physical address and virtual machine

hfence_gvma_all^⚠Experimental

Hypervisor memory management fence for all virtual machines and guest physical addresses

hfence_gvma_gaddr^⚠Experimental

Hypervisor memory management fence for guest physical address

hfence_gvma_vmid^⚠Experimental

Hypervisor memory management fence for given virtual machine

hfence_vvma^⚠Experimental

Hypervisor memory management fence for given guest virtual address and guest address space

hfence_vvma_all^⚠Experimental

Hypervisor memory management fence for all guest address spaces and guest virtual addresses

hfence_vvma_asid^⚠Experimental

Hypervisor memory management fence for given guest address space

hfence_vvma_vaddr^⚠Experimental

Hypervisor memory management fence for given guest virtual address

hinval_gvma^⚠Experimental

Invalidate hypervisor translation cache for guest physical address and virtual machine

hinval_gvma_all^⚠Experimental

Invalidate hypervisor translation cache for all virtual machines and guest physical addresses

hinval_gvma_gaddr^⚠Experimental

Invalidate hypervisor translation cache for guest physical address

hinval_gvma_vmid^⚠Experimental

Invalidate hypervisor translation cache for given virtual machine

hinval_vvma^⚠Experimental

Invalidate hypervisor translation cache for given guest virtual address and guest address space

hinval_vvma_all^⚠Experimental

Invalidate hypervisor translation cache for all guest address spaces and guest virtual addresses

hinval_vvma_asid^⚠Experimental

Invalidate hypervisor translation cache for given guest address space

hinval_vvma_vaddr^⚠Experimental

Invalidate hypervisor translation cache for given guest virtual address

hlv_b^⚠Experimental

Loads virtual machine memory by signed byte integer

hlv_bu^⚠Experimental

Loads virtual machine memory by unsigned byte integer

hlv_d^⚠Experimental

Loads virtual machine memory by double integer

hlv_h^⚠Experimental

Loads virtual machine memory by signed half integer

hlv_hu^⚠Experimental

Loads virtual machine memory by unsigned half integer

hlv_w^⚠Experimental

Loads virtual machine memory by signed word integer

hlv_wu^⚠Experimental

Loads virtual machine memory by unsigned word integer

hlvx_hu^⚠Experimental

Accesses virtual machine instruction by unsigned half integer

hlvx_wu^⚠Experimental

Accesses virtual machine instruction by unsigned word integer

hsv_b^⚠Experimental

Stores virtual machine memory by byte integer

hsv_d^⚠Experimental

Stores virtual machine memory by double integer

hsv_h^⚠Experimental

Stores virtual machine memory by half integer

hsv_w^⚠Experimental

Stores virtual machine memory by word integer

nopExperimental

Generates the NOP instruction

pauseExperimental

Generates the PAUSE instruction

sfence_inval_ir^⚠Experimental

Generates the SFENCE.INVAL.IR instruction

sfence_vma^⚠Experimental

Supervisor memory management fence for given virtual address and address space

sfence_vma_all^⚠Experimental

Supervisor memory management fence for all address spaces and virtual addresses

sfence_vma_asid^⚠Experimental

Supervisor memory management fence for given address space

sfence_vma_vaddr^⚠Experimental

Supervisor memory management fence for given virtual address

sfence_w_inval^⚠Experimental

Generates the SFENCE.W.INVAL instruction

sinval_vma^⚠Experimental

Invalidate supervisor translation cache for given virtual address and address space

sinval_vma_all^⚠Experimental

Invalidate supervisor translation cache for all address spaces and virtual addresses

sinval_vma_asid^⚠Experimental

Invalidate supervisor translation cache for given address space

sinval_vma_vaddr^⚠Experimental

Invalidate supervisor translation cache for given virtual address

sm3p0Experimental

P0 transformation function as is used in the SM3 hash algorithm

sm3p1Experimental

P1 transformation function as is used in the SM3 hash algorithm

sm4edExperimental

Accelerates the round function F in the SM4 block cipher algorithm

sm4ksExperimental

Accelerates the key schedule operation in the SM4 block cipher algorithm

wfi^⚠Experimental

Generates the WFI instruction